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201	Opportunities and pitfalls of multi-core scaling using Hardware Transaction Memory∗ Zhaoguo Wang†, Hao Qian‡, Haibo Chen‡, Jinyang Li§ † School of Computer Science, Fudan University ‡ Institute of Parallel a Add to Reading List Source URL: news.cs.nyu.edu Language: English - Date: 2013-07-16 15:24:14 Computing Data Software transactional memory Rock Non-blocking algorithm CPU cache Transactional memory Parallel computing Linearizability Concurrency control Transaction processing Data management
202	Towards fine-grained adaptivity in web caches Olivier Aubert, Antoine Beugnard ENST de Bretagne, Brest, France February 1999 Abstract Add to Reading List Source URL: www.olivieraubert.net Language: English - Date: 2014-04-30 11:37:23 Web cache World Wide Web Representational state transfer Squid Web server Proxy server CPU cache Computing Cache Computer memory
203	Automatic Generation of Veriable Cache Coherence Simulation Models from High-level Specications A.J. Field, P.G. Harrison, K. Kanani fajf,pgh, Department of Computing Imperial College Add to Reading List Source URL: pubs.doc.ic.ac.uk Language: English - Date: 2011-11-14 07:17:02 Cache coherence Cache CPU cache Parallel computing Computing Cache coherency Computer hardware
204	Microsoft Word - A Novel Memory Metric and Measurement Methodology for Modern Memory System_TC 11.docx Add to Reading List Source URL: www.cs.iit.edu Language: English - Date: 2014-08-05 09:45:40 Computer architecture Computing Cache CPU cache Microprocessors Memory hierarchy Microarchitecture Acumem SlowSpotter Computer hardware Central processing unit Computer memory
205	Sprint: Speculative Prefetching of Remote Data Arun Raman Greta Yorsh Martin Vechev Add to Reading List Source URL: www.cs.technion.ac.il Language: English - Date: 2011-08-29 23:46:23 Windows XP CPU cache Cache Central processing unit Parallel computing Database Prefetcher Trie Computer program Computing Computer memory Computer hardware
206	Guardat: Enforcing data policies at the storage layer Anjo Vahldiek-Oberwagner1 Eslam Elnikety1 Aastha Mehta1 Peter Druschel1 Rodrigo Rodrigues2 Add to Reading List Source URL: www.mpi-sws.org Language: English - Date: 2015-03-25 05:15:59 Computer architecture File system ZFS Cache Solid-state drive ISCSI CPU cache Backup Btrfs Disk file systems Computing Computer hardware
207	PDF Document Add to Reading List Source URL: www.geocachealaska.org Language: English - Date: 2014-02-04 20:01:10 Geocoin Travel Bug Cache Hoarding Geokrety CPU cache Recreation Geocaching Human behavior
208	CoDEx: CoDesign for Exascale John Shalf, David Donofrio X-Stack PI Meeting May 28, Add to Reading List Source URL: xstackwiki.modelado.org Language: English - Date: 2014-05-28 15:38:12 Central processing unit Computer memory Exascale computing Computing CPU cache Cache
209	CHAPTER 4 A METHODOLOGY FOR THE Add to Reading List Source URL: pubs.doc.ic.ac.uk Language: English - Date: 2011-11-14 08:22:52 Computer architecture Cache CPU cache Conventional PCI Cell Bus sniffing Dragon protocol Cache coherency Computing Computer hardware
210	ROSS-ICBS Phase 2 Interface FAQ’s for ICBS Users Updated: October 20, 2011 [New content in this update is shown in blue text below] ALERTS:  When I see alerts (e.g. NWCG ISSUE FAILURE ALERT), am I required to go in Add to Reading List Source URL: icbs.nwcg.gov Language: English - Date: 2011-11-21 14:17:28 Cache CPU cache RoS Spring Computer architecture Computing Computer memory

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